The present invention relates to semiconductor integrated circuits and their manufacture. The invention is illustrated in an example with regard to the manufacture of a read only memory ("ROM") cell, and more particularly to the manufacture of a flash electrically-erasable programmable read only memory ("Flash EEPROM") cell, but it will be recognized that the invention has a wider range of applicability. Merely by way of example, the invention may be applied in the manufacture of other semiconductor devices such as mask ROMs, microcontrollers, microprocessors ("MICROs"), digital signal processors ("DSPs"), application specific integrated circuits, among others.
Read only memories (ROMs) and various methods of their manufacture are known in the art. In the fabrication of a ROM, particularly an EEPROM, it is often necessary to fabricate a storage cell that maintains data after the applied power is turned off, that is, a storage cell having almost permanent data characteristics. The storage cells are generally mass data storage files where each cell corresponds to the presence or absence of a stored charge on a "floating" gate of a storage cell transistor. Specifically, the storage cell includes at least two conducting layers, i.e., one conducting layer is the floating gate of the storage cell transistor, and the other conducting layer is the control gate for control of the cell operation. The floating gate is formed on a thin gate oxide formed on the substrate. The control gate is located above the floating gate, and the control gate and floating gate are isolated each other by a thin dielectric layer known as an "interpoly oxide", which may typically be composed of oxide/nitride/oxide ("ONO"). In some typical EEPROMs, data is programmed into the cells by applying a high voltage to the control gate to inject hot electrons (or tunnel electrons in some devices) into the floating gate. The process of programming data is often called coding. In coding, the charge is transferred from the silicon substrate through the thin gate oxide layer to the floating gate.
In EEPROMs, especially for flash EEPROMs, two different gate oxide thicknesses are required for optimized device performance. In such devices, it is generally critical to grow a high-quality, thin gate oxide (used as a tunneling oxide) in the storage cell and (used as a thin gate oxide) in some transistors in the periphery of the storage cell region in order to provide high driving capability for higher speed. Controlling the thickness of the thin gate oxide is crucial, especially since design rules for devices with gates are becoming increasingly smaller and require thinner gate oxides. Because high-voltage supplies are used, thicker gate oxides at the periphery of the storage cell region are needed to maintain device quality and reliability after long-term high voltage stress from the high voltages (e.g., up to or greater than .+-.12V) generated through a pumping circuit for the storage cell coding and/or erase. Therefore, implementing different field oxide thicknesses in EEPROM devices is an important aspect of the fabrication of high performance devices.
As merely an example, FIG. 1 is a cross-sectional view diagram 10 of isolation structures 15, 17 for a flash memory device made using a local oxidation of silicon (LOCOS) process. These isolation structures 15, 17 are generally made by forming a thickness of silicon dioxide 12 using an oxidation process, i.e., thermal treatment, overlying a silicon substrate 11. Each of the isolation structures include active device regions in between the isolation structures. A silicon nitride layer is commonly formed overlying the active cell regions to prevent growth of oxide in active regions during the oxidation process. The isolation structures include an isolation structure 13 for a flash cell region, e.g., active cell region. A high voltage active cell region is also required for high voltage devices, e.g, MOS devices. The high voltage active cell region is isolated by way of thick field isolation oxide region 15. The thick field isolation region is generally made by lengthening the time of oxidation to create the thicker isolation region 15.
Unfortunately, extending oxidation times lead to a problem commonly known as a "bird's beak." As merely an example, outside edges of field isolation structure 13 includes the bird's beak 17. The bird's beak limits the size or area of the active cell region, depending upon the amount the bird's beak encroaches into the active cell region. Additionally, a bird's beak from isolation structure 15 can extend to a bird's beak from isolation structure 21. Isolation structure 15 is adjacent to isolation structure 21. This forms a relatively thick region of silicon dioxide 19, which cannot be effectively used to form active devices thereon. To reduce the detrimental influence of the bird's beak, a width between isolation structures also can be increased. Increasing the width also increases the size of the active cell region, thereby increasing the overall size of the die. Increasing die size is generally an undesirable consequence of poor designs in the fabrication of integrated circuits.
From the above, it is seen that a technique for an improved integrated circuit device is highly desirable.